Data processor and IP module for data processor

ABSTRACT

In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P 0 ), which is subjected to the address translation by TLB, and areas (P 1  and P 2 ), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address. Since it is adapted so that the areas (P 1  and P 2 ), which are conventionally mapped fixedly by hardware, are subjected to the address translation by the DTLB, it is possible to extend a size of the physical address space later without changing the hardware.

This application is a continuation of U.S. application Ser. No.10/640,855, filed on Aug. 13, 2003.

FIELD OF THE INVENTION

The present invention relates to a data processor such as amicroprocessor, a DSP (digital signal processor) or the like, whichsupports a virtual memory management system, and more particularly totechniques for use therein that are applied to memory control having atranslation lookaside buffer (TLB) for address translation, and inparticular a plurality of TLBs.

BACKGROUND OF THE INVENTION

Typically, the virtual memory management system in a data processor is afunction devised to make effective use of the physical memory. When therequired memory size for execution of a particular process is less thanthe available physical memory, it is possible to carry out the processby mapping to the physical memory. However, when the memory sizerequired by the process is larger than the physical memory, the processtypically has to be divided so that only selected sub-portions aremapped to the physical memory as needed.

Typically, a system in which the mapping to the physical memory iscontrolled and carried out as a batch by an OS (Operating System) insuch a manner that the process itself is not aware of the mapping to thephysical memory is called a virtual memory management system.

In a virtual memory management system, a sufficiently large virtualmemory, as compared to the physical memory, is provided to allow theprocess to be mapped to the virtual memory. Because of this, even when aplurality of processes exist substantially simultaneously, each processoperates only on the virtual memory. An MMU (Memory Management Unit),which is ordinarily controlled by the OS, is adopted for the mappingfrom the virtual memory to the physical memory. The MMU updates thephysical memory so that virtual memory necessary for the process ismapped smoothly to the physical memory. The update of the physicalmemory is carried out between secondary memories. Hereinafter, anaddress space in the virtual memory will be referred to as virtualaddress space while an address space in the physical memory will bereferred to as physical address space.

Although it is possible to realize the function of the MMU via softwareonly, typically it is not efficient to carry out the translation viasoftware every time the process accesses the physical memory.Accordingly, a translation lookaside buffer (TLB) for performing addresstranslation is provided as part of the hardware to store frequently usedaddress translation information. The TLB can be considered as a cachefor the address translation information. When address translation iscarried out from the virtual memory to the physical memory using theMMU, if the translation information has not been registered in the TLB,the MMU issues a TLB miss exception and registers new addresstranslation information in the TLB. However, unlike the cache, when theaddress translation has failed, i.e., when the TLB miss exception isissued, the replacement of the address translation information isordinarily carried out via software.

It has been determined that problems exist when it is desired to expandthe physical memory in a virtual memory management system. As for thevirtual memory management system, it was initially assumed that only arelatively small physical address space was desired for the virtualaddress space from the viewpoint of actual cost and mounting space.However, owing to the tendency of large capacity and low cost of DRAM(Dynamic Random Access Memory) typically used for main memory, it hasbecome possible to allow a physical address space equivalent in size tothe typically desired virtual address space. As a result, in certainsituations it has become easier to extend the main memory as thephysical address space.

FIG. 7 illustrates an example of a conventional approach involving anallocation of a virtual address space to the physical address space. Inthis example, the virtual address space is defined via 32 bits while thephysical address space is defined via 29 bits. The size of the virtualaddress space depends on the bit length that handles the address. In a32-bit microprocessor, the virtual address space is an area of 4 G bytes(or“4 GB”), i.e., the 32nd power of 2. On the other hand, the physicaladdress space depends on the size for mounting actual memory and variousbus interfaces. For example, in a microprocessor having a physicaladdress space of 29 bits, the physical address space is an area of 512 Mbytes (0.5 GB); i.e., the 29th power of 2.

A buffer in which is registered address translation information to carryout address translation from the virtual address space to the physicaladdress space is the TLB. In the example of FIG. 7, a portion includedin the area P0 (2 GB) of the virtual address space is subjected to theaddress translation into the physical address space of 0.5 GB by theTLB. On the other hand, since P1 and P2, which follow P0, are the areasexcluded from the TLB translation, a physical address may be generatedvia a fixed address mapping system, whereby the upper 3 bits of thevirtual address is fixed to 0. Due to this, P1 and P2 are assumedrespectively to be 0.5 GB, the same as the physical address space.

The reason why P1 and P2 are assumed as the fixed address mapping systemis described below. In the example of FIG. 7, it has been describedabove that the area of P0 is subjected to address translation by theTLB. Herein, it is presumed that a TLB miss has occurred, whichindicates the fact that desired address translation information has notbeen registered in the TLB. In this case, the MMU generates a TLB missexception, and the OS registers new address translation information inthe TLB. The program that performs the TLB replacement is generallystored in a particular area where the virtual address is fixedly mappedin the physical address without being subjected to address translation.As an example, referring to FIG. 7, the program that performs the TLBreplacement may be allocated to area P2 of the virtual address. Thereason of the above is as described below. If it is adapted so thatareas P1 and P2 are also subjected to the address translation by theTLB, when a TLB miss has occurred, there is a possibility that the TLBreplacement program for processing the TLB miss cannot be accessed dueto a new TLB miss. Thus, in the virtual address system, the particularsoftware of the system may require a virtual address area for mapping afixed address in the physical address.

In the conventional system of FIG. 7, based on an assumption that thephysical address space maximum is 0.5 GB, the mapping of the virtualaddress space is determined. Since it is possible to perform a fixedaddress mapping from the space of P1 or P2 to any address in thephysical address space of 0.5 GB, there is no limitation on the fixedaddress mapping. On the other hand, when the physical address space isextended from 0.5 GB in the conventional system, since only the 0.5 GBwithin the extended physical address space is the area that allows thefixed address mapping, it is necessary to carry out the fixed addressmapping by selecting the area in the design of the hardware. However, aswill be discussed in more detail below, since the area requiring thefixed address mapping varies depending on the system, it typically isnecessary to customize the hardware of each system. As a result,typically it is difficult to flexibly cope with the extension of thephysical address. For example, since the fixed mapping area of P1 and P2is the hardware that sets the upper 3 bits of the virtual address to 0,the fixed mapping area of P1 and P2 is linked to 0.5 GB only at thestart of the physical address. Also, although P1 and P2 have a space of0.5 GB respectively, some applications do not need 0.5 GB for the fixedaddress mapping area. As will be discussed in more detail below inconnection with embodiments of the present invention, if it is possibleto use a page subjected to the fixed address mapping, and a pagesubjected to the address translation, while appropriately separating thepages from each other, it is possible to use the virtual address spacemore efficiently.

It is an object of the invention to provide systems and methods for adata processor capable of extending the size of, mainly, the physicaladdress space. Another object of the invention is to provide systems andmethods for ensuring that a supervisor program performing TLBreplacement does not issue misses to the TLB. Furthermore, it is anotherobject of the present invention to provide a feature allowing the userswho may not use the MMU to extend the size of the physical addressspace.

SUMMARY OF THE INVENTION

In accordance with preferred embodiments of the present invention, adata processor preferably includes a central processing unit (“CPU”) andan address translation unit (“ATU”) that preferably receives a virtualaddresses output from the central processing unit and outputs a physicaladdress, wherein the address translation unit preferably includes afirst translation lookaside buffer (“UTLB”), a second translationlookaside buffer (“DTLB”), and a control circuit (“TLB_CTL”) forselecting one of the first and second translation lookaside buffers andperforming address translation in accordance with an area of an addressspace in the virtual address.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and other advantages of the present invention willbecome more apparent by describing in detail the preferred embodimentsof the present invention with reference to the attached drawings inwhich:

FIG. 1 is an exemplary block diagram of a data processor according to apreferred embodiment of the present invention and having a plurality oftranslation lookaside buffers (TLBs); utilized in accordance withcertain embodiments of the present invention;

FIG. 2 is an exemplary configuration diagram of a first translationlookaside buffer, utilized in accordance with certain embodiments of thepresent invention;

FIG. 3 is an exemplary configuration diagram of a second translationlookaside buffer, utilized in accordance with certain embodiments of thepresent invention;

FIG. 4 is an exemplary flowchart of physical address generation,utilized in accordance with certain embodiments of the presentinvention;

FIG. 5 is an exemplary diagram mapping from a 32-bit virtual addressspace to a 29-bit physical address space, utilized in accordance withcertain embodiments of the present invention;

FIG. 6 is an exemplary diagram mapping from a 32-bit virtual addressspace to a 32-bit physical address space, utilized in accordance withcertain embodiments of the present invention; and

FIG. 7 is an exemplary diagram mapping from a 32-bit virtual addressspace to a 29-bit physical address space, in accordance with the priorart.

DETAILED DESCRIPTION OF EXEMPLARY PREFERRED EMBODIMENTS

Hereinafter, referring to the accompanying drawings, a description as toa data processor (or information processing system) and the mode ofcertain aspects of the preferred embodiments of the system will be made.The circuit elements constituting each block of the embodimentpreferably are formed on a semiconductor substrate such as singlecrystal silicon by means of a technique of semiconductor integratedcircuit such as well-known CMOS (complementary MOS transistor) andbipolar transistor or the like, though the elements are not particularlylimited thereto. Also, the invention preferably may be realized as anintellectual property (“IP”) or design data module (either soft IP orhard IP) as all or a portion of the design data for forming asemiconductor integrated circuit. The IP module preferably is stored inan information-recording medium, and preferably may be subjected to atrade and/or transfer via a telecommunication line, data network or thelike.

FIG. 1 illustrates an example of a data processor as an exemplarypreferred embodiment of the invention. FIG. 1 is a block diagram of adata processor 1000 illustrating an address translation unit ATUaccording to the invention. The data processor 1000 preferably isconnected to a central processing unit CPU via a logical address busLAB, and preferably is connected to a memory controller MEM_CTL via aphysical address bus PAB. The address translation unit ATU preferablyincludes a first translation lookaside buffer UTLB, a second translationlookaside buffer DTLB, an address chop circuit CHOP that preferablygenerates in a fixed manner a physical address from a virtual address, aTLB control circuit TLB_CTL that preferably controls the above, and aphysical address control selector SEL. The DTLB, the TLB_CTL, and theSEL preferably are included in the address translation unit ATU.Preferably, the first translation lookaside buffer UTLB performs addresstranslation with respect to both data access and instruction access. Thethird translation lookaside buffer OTLB preferably is provided as atranslation lookaside buffer for operands. Reference symbol and numeralsOTLB, 106, and 107 denote optional component elements for alternativeembodiments as indicated with dotted lines in FIG. 1, and thedescription thereof will be made below.

Taking the memory access operation of the data processor 1000 as anexample, a generating flow of the physical address from the virtualaddress will be described. The central processing unit CPU preferablyincludes a control unit and an execution unit, which are not shown inthe figures. When performing a memory access, a virtual address 100 isissued by the CPU to the address translation unit ATU.

The TLB control circuit TLB_CTL preferably decodes a part of the virtualaddress 100 and determines whether (A) output signal 101 of the UTLBshould be selected as the physical address using the address translationby the first translation lookaside buffer UTLB, (B) output signal 102 ofDTLB should be selected as the physical address using the addresstranslation by the second translation lookaside buffer DTLB, or (C)output signal 103 of the CHOP should be selected as physical addressusing the address chop circuit CHOP, to control the physical addresscontrol selector SEL. At this time, the TLB control circuit TLB_CTL alsopreferably refers to enable information MMU_ENB_REG of the MMU andenable information DTLB_ENB_REG of the DTLB to control the physicaladdress control selector SEL. The generated physical address 104preferably is sent to the memory control circuit MEM_CTL and the memoryaccess preferably is carried out.

FIG. 2 and FIG. 3 illustrate a further detailed exemplary configurationof the first translation lookaside buffer UTLB and the secondtranslation lookaside buffer DTLB, respectively. The UTLB illustrated inFIG. 2 is a configuration of an exemplary TLB, which outputs thephysical address of an entry corresponding to the compared and inputvirtual address 100 in accordance with the virtual address and thephysical address registered via software. In accordance with anexemplary preferred embodiment of the present invention, theconfiguration of the TLB preferably includes 64 entries; each entrypreferably includes approximately 64 bits including fields of a virtualpage number (VPN), an address space identifier (ASID), a valid bit (V),a physical page number (PPN), a page size bit (SZ), and others (OTHER).Examples of OTHER include a change between cacheable and non-cacheablein units of page of the TLB, and a change between copy-back andwrite-through modes.

FIG. 3 illustrates a configuration of the second translation lookasidebuffer DTLB in an exemplary TLB, which outputs the physical address ofan entry which corresponds to the compared and input virtual address 100in accordance with the virtual address and the physical addressregistered via software. Compared to the above-described UTLB, thenumber of the entries of the DTLB preferably is smaller. In accordancewith an exemplary preferred embodiment of the present invention, theDTLB preferably includes 16 entries and each entry preferably includesapproximately 20 bits. Each entry preferably includes the fields of avirtual page number (VPN), an valid bit (V), a physical page number(PPN), a page size bit (SZ), and others (OTHER). Compared to the UTLB,since the number of entries is approximately one fourth and the bits ofeach entry is approximately one third, it is possible to mount the DTLBin an extremely small TLB. The reason of the above is that, since theDTLB performs the mapping in a larger page unit, by adapting the pagesize handled by the TLBs to be different between the UTLB and the DTLBthe number of the entries can be smaller, and furthermore, the fieldwidth of the VPN and the PPN included in each entry can be smaller.

The address chop circuit CHOP in FIG. 1, in accordance with an exemplarypreferred embodiment of the present invention,. preferably outputsvirtual address 100 as the physical address 103, and preferably has afunction by which unnecessary upper bits generated due to a differencein size between the virtual address space and the physical address spaceare set to 0. As an example which will be described later with regardsto FIG. 5, a virtual address space of 4 GB can be mapped to a physicaladdress space of 0.5 GB, the CHOP is a module that preferably sets theupper 3 bits of the 32 bits to 0 while the lower 29 bits therefrompreferably are output as the physical address. Generally, in accordancewith such embodiments, the described operation of the CHOP is a functioninherent in the hardware, i.e., the CHOP maps a virtual address spacearea fixedly to a physical address space area via the hardware.

FIG. 4 is an exemplary flowchart that determines, based on the virtualaddress issued from the CPU (e.g., in accordance with the control of TLBcontrol circuit TLB_CTL) in what manner the physical address should begenerated, i.e., by the first translation lookaside buffer UTLB, thesecond translation lookaside buffer DTLB, or the CHOP.

The TLB control circuit TLB_LCTL preferably decodes the upper bits ofthe virtual address output from the CPU, and determines the area (e.g.,any one of P0, P1, and P2 or the like) in the virtual address (S1). Ifthe virtual address 100 is within an area which is subjected to theaddress translation by the MMU. (e.g., within P0 in the example of FIG.5, which will be described further below), and if the MMU is enabled(e.g., MMU_ENB_REG in the TLB_CTL is set to “enable”), the TLB controlcircuit TLB_CTL preferably selects the output signal 101 of the UTLB asthe physical address 104 (i.e., S2, S3, and S5). If the virtual address100 is not within an area which is subjected to the address translationby the MMU (e.g., within P1 and P2 in the example of FIG. 5, which willbe described further below), and if the DTLB is enabled (e.g., when theDTLB_ENB_REG in the TLB_CTL is set to “enable”), the output signal 102of the DTLB preferably is selected as the physical address 104 (i.e.,S2, S4, and S7). In other cases, the output signal 103 of the CHOPpreferably is selected as the physical address 104 (i.e., S6). Notethat, immediately after resetting the data processor 1000, when the MMUand the DTLB are not enabled, since no translation information is set inthe TLB, a physical address preferably is generated fixedly by the CHOPoutput.

FIG. 4 illustrates an example in which the physical address preferablyis selected via the control of the TLB_CTL after both of the UTLB andthe DTLB have carried out the address translation. However, since theTLB_CTL preferably detects which of the UTLB and the DTLB is selected,low power control may be adopted by carrying out such control so thatonly the necessary TLB is activated. Thus, in alternative embodiments,the TLB_CTL may be coupled to the UTLB and DTLB to selectively activatethe UTLB or the DTLB when the output thereof is to be selected togenerate the physical address.

FIG. 5 illustrates a 32-bit virtual address space mapped to a 29-bitphysical address space as an example in accordance with one exemplarypreferred embodiment of the present invention. In the addresstranslation system illustrated in FIG. 5, area P0 of 2 G bytes is thearea to be subjected to UTLB translation, and the following areas P1 andP2 of 0.5 G bytes are areas to be subjected to DTLB translation. Due inpart to the second translation lookaside buffer DTLB (which is providedin accordance with the present invention), the address translation ofareas P1 and P2 is carried out in accordance with the contentsregistered in the DTLB without being limited to fixed mapping. Comparedto the conventional example illustrated in FIG. 7, in which areas P1 andP2 are mapped fixedly to the physical address space, certain benefits ofthe present invention are achieved as compared with the conventionalapproach.

By allowing the logical address of a supervisor program (e.g., addresstranslation miss handling routine), which performs replacement of theTLB, as well as allowing the DTLB entry, which is used to translate thelogical address of an address translation table or the like which thesupervisor program accesses, to be resident in the physical address, itis possible to avoid TLB misses during the execution of TLB replacementvia the supervisor program. That is to say, control of the entries ofthe DTLB is made so that the physical address, which is stored in theDTLB entries, is not rewritten even when the second translationlookaside buffer issues an address translation miss. For example, atypical address translation table may be allocated with approximately 8bytes per page; assuming that one page is 4 KB, a capacity of 1 MB isrequired for the physical address of 0.5 GB. Since the page size of theDTLB is the range from 16 MB to 0.5 GB, it is possible to allow thisamount to be resident in one entry. However, in the case that one pageis 4 KB, 256 entries are required to allow this amount to be resident,which may not be practical since a large-capacity TLB is required.

As for the parts of areas P1 and P2 of the above-described TLB (whichare not used for the replacement), because in certain examples it is notalways necessary to avoid any TLB misses, the areas may be subjected tothe address translation. In these examples, the remaining entries notallowed to rewrite a physical address that may be stored upon an addresstranslation miss of the DTLB preferably are allowed to rewrite aphysical address that may be stored in the entries upon an addresstranslation miss. Accordingly, by utilizing a large page size. of theDTLB, it is possible to make the DTLB to perform a function tocomplement the UTLB, which preferably is able to perform a finer degreeof mapping.

In the prior art example illustrated in FIG. 7, area P1 is a cacheablearea (which makes use of the cache), while area P2 is a non-cacheablearea (which does not use the cache). In this example, both of areas P1and P2 are subjected to a fixed address mapping. However, in the case ofthe DTLB in accordance with the present invention, by assigning acacheable attribute to the OTHER field of the DTLB, it is possible tocontrol the DTLB while preferably distinguishing between a cacheablearea and a non-cacheable area (e.g., which does not use the cache) to afiner degree; i.e., in units of pages that are subjected to the addresstranslation by the DTLB.

In FIG. 5, areas P3 and P4 preferably are further included. P3preferably is an area subjected to address translation by the UTLB, andpreferably is handled in the same manner as area P0. On the other hand,area P4 preferably is an area subjected to address translation by theDTLB, and accordingly it preferably is handled in the same manner asareas P1 and P2. In FIG. 5, the relationship of the address mapping ofP3 and P4 is omitted for purposes of clarity.

FIG. 6 illustrates mapping from a 32-bit virtual address space to a32-bit physical address space as an example of other embodiments of thepresent invention. In the address translation method illustrated in FIG.6, similarly to the previously described FIG. 5, area P0 of 2 G bytes isthe area that is subjected to UTLB translation; the following areas P1and P2 of 0.5 G bytes respectively are the areas that are subjected toDTLB translation. Because of the use of the DTLB, it is possible tocarry out the mapping from the virtual address spaces of 1 G bytes(including areas P1 and P2) to the physical address space of 4 G bytes.An example of the mapping of the UTLB and the DTLB is illustrated inFIG. 6. In this example, although the mapping by the UTLB is mapping ofa page size of 4 KB, it is shown that a larger area mapping (a largearea of 128 MB, for example, which is equivalent to a quarter of thearea of P1, is mapped via one entry) is carried out by the DTLB. In thisphysical address space example, various kinds of spaces such as mainmemory space (e.g., SDRAM or the like), boot ROM space, PCI space, I/Ospace and coprocessor space or the like are included, and each may be aspace of varying size from several kilobytes to several gigabytes. Byproviding the DTLB with various page sizes and entries of sufficientnumber to cover the areas of P1 and P2, it is possible to allow allmapping information of the areas of the respective spaces (necessary forfixed mapping) to be resident in the DTLB. Further, in a configurationin which an MMU is not used, it is possible to adopt a system in whicharea P0 of 2 G bytes is mapped to the physical address space of 2 Gbytes while the areas of 1 G bytes (including P1 and P2 areas) aremapped to the physical address space of 2 G bytes using the DTLB.

The areas P3 and P4 in FIG. 6 preferably are handled in the same manneras areas P3 and P4 described in conjunction with FIG. 5. For clarity,the corresponding relationship of the address mapping of areas P3 and P4are not shown in FIG. 6.

In accordance with certain alternative embodiments of the presentinvention, data processor may be provided that has a configuration thatincludes a micro translation lookaside buffer for operand OTLB (anexample of which is illustrated in FIG. 1 marked with the dotted line).In certain situations when it may be difficult to use a UTLB (e.g., dueto a problem of electric power or speed), a micro TLB may be used.Although a mode wherein the UTLB and the DTLB have a micro TLB may bethe simplest mode, in the example shown in FIG. 1, the OTLB as a microTLB excludes the need for the micro TLB for the DTLB. That is to say,(1) since the micro TLB is of a small capacity, even when the functionsof both the UTLB and the DTLB are incorporated, there preferably are noproblems in terms of speed; (2) since the micro TLB is a copy of theUTLB and the DTLB, it is renewed automatically by the hardware when anymiss has occurred; and (3) even when the copy of the DTLB does notreside in the OTLB, since the necessary entry can be copied from theDTLB by the hardware, another TLB miss does not occur. Accordingly, evenwhen a copy of the DTLB is held, the OTLB may be a typical TLB as it is,in which preferably a TLB miss is allowed. When a large page size isprovided to the DTLB but not to the UTLB, an OTLB in accordance with thepresent invention, is obtained.

The practical operation of the OTLB shown in FIG. 1 is as describedbelow. As in the case that the OTLB is not used, the central processingunit CPU issues a virtual address 100 to the address translation unitATU. The first translation lookaside buffer UTLB, the second translationlookaside buffer DTLB, the address chop circuit CHOP, and the microtranslation lookaside buffer for operand OTLB, preferably translate thevirtual address 100 into a physical address. When the OTLB is hit, theTLB control circuit TLB_CTL preferably selects an OTLB output 106responding to a hit signal 107. If a miss occurs, the output from theUTLB, the DTLB, or the CHOP preferably is selected as the physicaladdress based in part on the decode result of a part of the virtualaddress 100. In order to reduce power consumption, only when an OTLBmiss has occurred, certain aspects of the present invention make itpossible to make one or more of the other translation lookaside buffersoperate. In additional variations, one or more of the other translationlookaside buffers is made to operate by decoding the virtual address 100beforehand. Upon an OTLB miss, in preparation for the next access, thehit entry of the UTLB or the DTLB preferably is copied to the OTLB. Atthis time, based on an algorithm of an LRU (i.e., the least recentlyused entry is subjected to the replacement) or the like, an object to besubjected to replacement preferably is selected. When a miss hasoccurred for both the OLTB and the UTLB, a TLB miss exception preferablyis generated. As described above, the miss preferably does not occur forthe DTLB.

Although certain embodiments in which the invention is applied to amicro translation lookaside buffer for operand OTLB (e.g., as shown inFIG. 1), it is possible to apply certain aspects of the presentinvention to a micro translation lookaside buffer for an instructionITLB. In this case, while responding to an instruction fetch operationof the central processing unit CPU, the ITLB preferably is made tooperate selectively, and preferably is allowed to operate addresstranslation processing in parallel with the UTLB and the DTLB. In partbecause of this, the address translation at the instruction fetchoperation preferably can be carried out at a higher speed.

Based on certain features of the embodiments described herein, theeffect obtained because of the invention disclosed in this applicationwill be described briefly below.

By using the first translation lookaside buffer UTLB and the secondtranslation lookaside buffer DTLB separately depending on the area ofthe virtual address (e.g., as shown in FIG. 1), the UTLB preferablyundertakes the function of the TLB in the conventional technique whilethe DTLB preferably undertakes a function that substitutes for theconventional technique where the physical address is generated in amanner of fixed mapping. By programming the DTLB, a supervisor programarea (typified by a program for performing replacement of the TLB),preferably can generate the physical address to the TLB in accordancewith the registered address translation information without causing anymisses. In prior art approaches, since the area other than the areawhich is subjected to the TLB translation is subjected to the fixedmapping by hardware, it typically is impossible to extend/upgrade thesize of the physical address space later without changing the hardwareon the processor core. However, in the presently described techniquesusing the DTLB according to the invention, it is possible toextend/upgrade the size of the physical address space later withoutchanging the hardware of the processor since it is possible to programthe DTLB. Furthermore, it is not always necessary that the firsttranslation lookaside buffer UTLB and the second translation lookasidebuffer DTLB handle the same page size. Since the DTLB preferably canperform the mapping of the virtual address space to the physical addressspace in a larger unit, it is possible to reduce the number of theentries of the DTLB. Accordingly, since it is possible to reduce thenumber of the address translation bits held by the DTLB by performingthe mapping in a larger unit, it is possible to largely reduce the sizeof the hardware necessary for mounting the DTLB compared to the ordinaryTLB, and at the same time, it is possible to generate the physicaladdress at a higher speed.

Also, by stratifying the TLB, even when a configuration having a microTLB (e.g., with a small number of entries for instruction fetch oroperand access), the technique according to the invention is applicablein the same manner as described above. Even when pages with differentsizes are handled by the UTLB and the DTLB, preferably it is possiblefor the micro TLB to hold entries from both of the UTLB and the DTLB ina mixed manner.

By employing a processor core using a DTLB according to certain aspectsof the present invention, users who do not use the MMU preferably canalso utilize a benefit owing to the extension of the physical addressspace size.

Furthermore, by providing associated information to the OTHER field ofthe DTLB, it preferably is possible to perform various controls moreflexibly. For example, it is possible to control the switching betweencacheable and non-cacheable, between copy-back and write-through, or thelike. In certain prior art approaches the page size unit of the DTLBmight determine these characteristics in a larger space unit.

A processor core having a 32-bit virtual address space, to which thesystem of the invention is applied, is a processor core preferablyhaving a large flexibility in the address translation method. Inaddition to the examples illustrated in FIG. 5 and FIG. 6, it isapplicable to a 30-bit-1 GB physical address space and a 31-bit-2 GBphysical address space. As demonstrated in the above description, whendeveloping a system mounted with a processor core, in which an addresstranslation unit according to the invention is adopted, it preferably ispossible to determine a suitable size of the physical address space andthe address map of the system during a development phase irrespective ofthe hardware features within the processor core. It is thereforepossible to prepare a very flexible processor core.

According to the invention, it is possible to extend the physicaladdress space in a data processor of a virtual memory management systemeasily.

As will be understood by a person of ordinary skill in the present art,the examples discussed here are representative of the full spirit andscope of the present invention. Additional variations, some of which aredescribed here, incorporate many aspects of the present invention.

Although the invention has been described in conjunction with specificpreferred and other embodiments, it is evident that many substitutions,alternatives and variations will be apparent to those skilled in the artin light of the foregoing description. Accordingly, the invention isintended to embrace all of the alternatives and variations that fallwithin the spirit and scope of the appended claims. For example, itshould be understood that, in accordance with the various alternativeembodiments described herein, various systems, and uses and methodsbased on such systems, may be obtained. The various refinements andalternative and additional features also described may be combined toprovide additional advantageous combinations and the like in accordancewith the present invention. Also as will be understood by those skilledin the art based on the foregoing description, various aspects of thepreferred embodiments may be used in various subcombinations to achieveat least certain of the benefits and attributes described herein, andsuch subcombinations also are within the scope of the present invention.All such refinements, enhancements and further uses of the presentinvention are within the scope of the present invention.

1. A microprocessor, comprising: a central processing unit; and anaddress translation unit that receives virtual addresses output from thecentral processing unit and outputs physical addresses; wherein theaddress translation unit includes a first translation lookaside buffer,a second translation lookaside buffer, and a control circuit forselecting one of the first and second translation lookaside buffers,wherein the control circuit selectively controls operation of the firstand second translation lookaside buffers to selectively output aphysical address based on stored enable information, wherein the controlcircuit includes storage for storing the stored enable information and aselector coupled to outputs of the first translation lookaside bufferand the second translation lookaside buffer, wherein the selectorselectively operates to output the physical address based on the storedenable information, wherein upon reset of the date processor the storedenable information controls the selector so that it does not output anyphysical address from either the first translation lookaside buffer orthe second translation lookaside buffer, wherein the address translationunit performs address translation in accordance with an area of avirtual address space of a virtual address received from the centralprocessing unit.
 2. A microprocessor according to claim 1, wherein eachof the first and second translation lookaside buffers has a plurality ofentries for holding physical addresses associated with respectivevirtual addresses for performing the address translation, wherein thecentral processing unit is capable of accessing a first virtual addressspace and a second virtual address space included in the virtual addressspace, wherein the first translation lookaside buffer translates avirtual address of the first virtual address space to a physicaladdress, and wherein the second translation lookaside buffer translatesa virtual address of the second virtual address space to a physicaladdress.
 3. A microprocessor, comprising: a central processing unit; andan address translation unit that receives virtual addresses output fromthe central processing unit and outputs physical addresses; wherein theaddress translation unit includes a first translation lookaside buffer,a second translation lookaside buffer, and a control circuit forselecting one of the first and second translation lookaside buffers,wherein the control circuit selects one of the first and secondtranslation lookaside buffers to output a physical address based onstored enable information, wherein the address translation unit performsaddress translation in accordance with an area of a virtual addressspace of a virtual address received from the central processing unit,wherein each of the first and second translation lookaside buffers has aplurality of entries for holding physical addresses associated withrespective virtual addresses for performing the address translation,wherein the central processing unit is capable of accessing a firstvirtual address space and a second virtual address space included in thevirtual address space, wherein the first translation lookaside buffertranslates a virtual address of the first virtual address space to aphysical address, wherein the second translation lookaside buffertranslates a virtual address of the second virtual address space to aphysical address, wherein first entries of the plurality of entries inthe second translation lookaside buffer are controlled to be disabledfrom rewriting if the second translation lookaside buffer detects anaddress translation miss, and wherein second entries of the plurality ofentries in the second translation lookaside buffer are controlled to beenabled for rewriting if the second translation lookaside buffer detectsan address translation miss.
 4. A microprocessor according to claim 3,wherein the first entries store physical addresses for an addresstranslation miss handling routine.
 5. A microprocessor according toclaim 4, wherein it is determined whether or not the plurality ofentries in the second translation lookaside buffer should be rewrittenat an address translation miss in accordance with the addresstranslation miss handling routine.
 6. A microprocessor according toclaim 1, wherein the control circuit decodes upper bits of a virtualaddress output from the central processing unit and selects one of thefirst and second translation lookaside buffers in accordance with adecode result.
 7. A microprocessor according to claim 1, wherein theaddress translation unit further includes a selection circuit to which afirst output of the first translation lookaside buffer and a secondoutput of the second translation lookaside buffer are input, wherein theselection circuit selects one of the first and second outputs inaccordance with a control signal of the control circuit.
 8. Amicroprocessor according to claim 1, wherein the address translationunit further includes an address chop circuit that fixedly forms aphysical address from a virtual address when both of the first andsecond translation lookaside buffers are disabled.
 9. A microprocessoraccording to claim 1, wherein a page size of the first translationlookaside buffer is different from a size of the second translationlookaside buffer.
 10. A microprocessor, comprising: a central processingunit; and an address translation unit that receives virtual addressesoutput from the central processing unit and outputs physical addresses;wherein the address translation unit includes a first translationlookaside buffer, a second translation lookaside buffer, and a controlcircuit for selecting one of the first and second translation lookasidebuffers, wherein the control circuit selects one of the first and secondtranslation lookaside buffers to output a physical address based onstored enable information, wherein the address translation unit performsaddress translation in accordance with an area of a virtual addressspace of a virtual address received from the central processing unit,wherein each of the first and second translation lookaside buffers has aplurality of entries for holding physical addresses associated withrespective virtual addresses for performing the address translation,wherein the central processing unit is capable of accessing a firstvirtual address space and a second virtual address space included in thevirtual address space, wherein the first translation lookaside buffertranslates a virtual address of the first virtual address space to aphysical address, wherein the second translation lookaside buffertranslates a virtual address of the second virtual address space to aphysical address, wherein the number of the plurality of entriesincluded in the first translation lookaside buffer is adapted so as tobe larger than the number of the plurality of entries included in thesecond translation lookaside buffer, and wherein a page size when thefirst translation lookaside buffer translates the virtual address of thefirst virtual address space to the physical address is adapted so as tobe smaller than a page size when the second translation lookaside buffertranslates the virtual address of the second virtual address space tothe physical address.
 11. A microprocessor, comprising: a centralprocessing unit; and an address translation unit that receives virtualaddresses output from the central processing unit and outputs physicaladdresses; wherein the address translation unit includes a firsttranslation lookaside buffer, a second translation lookaside buffer, anda control circuit for selecting one of the first and second translationlookaside buffers, wherein the control circuit selects one of the firstand second translation lookaside buffers to output a physical addressbased on stored enable information, wherein the address translation unitperforms address translation in accordance with an area of a virtualaddress space of a virtual address received from the central processingunit, wherein each of the first and second translation lookaside buffershas a plurality of entries for holding physical addresses associatedwith respective virtual addresses for performing the addresstranslation, wherein the central processing unit is capable of accessinga first virtual address space and a second virtual address spaceincluded in the virtual address space, wherein the first translationlookaside buffer translates a virtual address of the first virtualaddress space to a physical address, wherein the second translationlookaside buffer translates a virtual address of the second virtualaddress space to a physical address, wherein the address translationunit further includes a third translation lookaside buffer having aplurality of entries for holding predetermined physical addressesassociated with predetermined virtual addresses for performing addresstranslation, and wherein the plurality of entries of the thirdtranslation lookaside buffer are capable of storing both a copy of apart of the entries of the plurality of entries in the first addressbuffer and a copy of a part of the entries of the plurality of entriesin the second address buffer.
 12. A microprocessor according to claim11, wherein the third address buffer is capable of operating selectivelyin accordance with an instruction fetch operation of the centralprocessing unit so as to perform address translation processing inparallel with the first and second translation lookaside buffers.
 13. Amicroprocessor, comprising: a central processing unit; and an addresstranslation unit that receives virtual addresses output from the centralprocessing unit and outputs physical addresses; wherein the addresstranslation unit includes a first translation lookaside buffer forperforming address translation of a first virtual address space in thevirtual addresses, a second translation lookaside buffer for performingaddress translation of a second virtual address space in the virtualaddresses, and a control circuit for selecting one of the first andsecond translation lookaside buffers in accordance with whether avirtual address output from the central processing unit is in the firstvirtual address space or the second virtual address space, wherein thecontrol circuit selectively controls operation of the first and secondtranslation lookaside buffers to selectively output a physical addressbased on stored enable information, wherein the control circuit includesstorage for storing the stored enable information and a selector coupledto outputs of the first translation lookaside buffer and the secondtranslation lookaside buffer, wherein the selector selectively operatesto output the physical address based on the stored enable information,wherein upon reset of the date processor the stored enable informationcontrols the selector so that it does not output any physical addressfrom either the first translation lookaside buffer or the secondtranslation lookaside buffer.
 14. A microprocessor according to claim13, wherein each of the first and second translation lookaside buffersincludes a plurality of entries for holding physical addressesrespectively associated with virtual addresses for performing addresstranslation.
 15. A microprocessor according to claim 13, wherein thesecond translation lookaside buffer includes entries for an addresstranslation miss handling routine of the first translation lookasidebuffer, wherein the entries for the address translation miss handlingroutine are disabled from rewriting.
 16. An IP module includinginformation of a microprocessor module, comprising: data for defining anaddress translation unit for receiving virtual addresses output from acentral processing unit and outputting physical addresses, wherein theaddress translation unit includes a first translation lookaside buffer,a second translation lookaside buffer, and a control circuit forselecting one of the first and second translation lookaside buffers,wherein the address translation unit performs address translation inaccordance with an area of a virtual address space of a virtual addressreceived from the central processing unit, wherein the control circuitselectively controls operation of the first and second translationlookaside buffers to selectively output a physical address based onstored enable information, wherein the control circuit includes storagefor storing the stored enable information and a selector coupled tooutputs of the first translation lookaside buffer and the secondtranslation lookaside buffer, wherein the selector selectively operatesto output the physical address based on the stored enable information,wherein upon reset of the date processor the stored enable informationcontrols the selector so that it does not output any physical addressfrom either the first translation lookaside buffer or the secondtranslation lookaside buffer.
 17. An IP module according to claim 16,wherein each of the first and second translation lookaside buffers has aplurality of entries for holding physical addresses associated withrespective virtual addresses for performing the address translation,wherein the central processing unit is capable of accessing a firstvirtual address space and a second virtual address space included in thevirtual address space, wherein the first translation lookaside buffertranslates a virtual address of the first virtual address space to aphysical address, and wherein the second translation lookaside buffertranslates a virtual address of the second virtual address space to aphysical address.
 18. An IP module including information of amicroprocessor module, comprising: data for defining an addresstranslation unit for receiving virtual addresses output from a centralprocessing unit and outputting physical addresses, wherein the addresstranslation unit includes a first translation lookaside buffer, a secondtranslation lookaside buffer, and a control circuit for selecting one ofthe first and second translation lookaside buffers, wherein the addresstranslation unit performs address translation in accordance with an areaof a virtual address space of a virtual address received from thecentral processing unit, wherein the control circuit selects one of thefirst and second translation lookaside buffers to output a physicaladdress based on stored enable information, wherein each of the firstand second translation lookaside buffers has a plurality of entries forholding physical addresses associated with respective virtual addressesfor performing the address translation, wherein the central processingunit is capable of accessing a first virtual address space and a secondvirtual address space included in the virtual address space, wherein thefirst translation lookaside buffer translates a virtual address of thefirst virtual address space to a physical address, and wherein thesecond translation lookaside buffer translates a virtual address of thesecond virtual address space to a physical address, wherein firstentries of the plurality of entries in the second translation lookasidebuffer are controlled to be disabled from rewriting if the secondtranslation lookaside buffer detects an address translation miss, andwherein second entries of the plurality of entries in the secondtranslation lookaside buffer are controlled to be enabled for rewritingif the second translation lookaside buffer detects an addresstranslation miss.
 19. A microprocessor according to claim 1, wherein thecontrol circuit selectively activates the first and second addresstranslation lookaside buffers, wherein power consumption of themicroprocessor is selectively controlled.
 20. A microprocessor accordingto claim 10, wherein the control circuit selectively activates the firstand second address translation lookaside buffers, wherein powerconsumption of the microprocessor is selectively controlled.